This book focuses on the exploration of various power optimization methods for video processing SoCs. An existing application, a video pixel processor for high-end television sets, is used as a case study. Furthermore, the influence of a recently developed communication infrastructure, Network-on-Chip (NoC), on power dissipation is analyzed. An extensive power analysis is performed on the Network Interface (NI), a key part of the NoC. The results have been applied to the recent design of a NoC-based video pixel processor and an alternative implementation is proposed that promises to reduce the power dissipation by about 50%.