AHA-BUCH

Low Power Networks-on-Chip
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Low Power Networks-on-Chip

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ISBN-13:
9781441969101
Einband:
Buch
Erscheinungsdatum:
01.11.2010
Seiten:
287
Autor:
Cristina Silvano
Gewicht:
615 g
Format:
244x167x28 mm
Sprache:
Englisch
Beschreibung:

With power consumption now a key design constraint, recent years have seen growing research interest in these networks as an architectural solution for high-speed data transfer. This single-source reference covers some of the most important design techniques.
Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures

Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect

Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings
Network-on-Chip Power Estimation.- Timing.- synchronous/asynchronous communication.- Network-on-Chip link design.- Topology exploration.- Network-on-Chip support for CMP/MPSoCs.- Network design for 3D stacked logic and memory.- Beyond the wired Network-on-Chip.
In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issuesstill represent one of the limiting factors in integrating multi- and many-cores
on a single chip.
This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.

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