Low-Power Design and Power-Aware Verification

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Progyna Khondkar
420 g
244x162x20 mm

Complete Low-power design and verification engineering reference book - Required by a wide range of audience - verification engineer, design engineer, engineering policy maker, EDA tool developer, academic researcher and senior students (undergrad/grad) of computer science, electrical engineering, etc.
1 Introduction 2 Background 2.1 The Power of Intent 2.2 The Abstraction of UPF 3 Modeling UPF 3.1 Fundamental Constructs of UPF 3.1.1 UPF Power Domain and Domain Boundary 3.1.2 UPF Power Supply and Supply Networks 3.1.3 UPF Power Stages 3.1.4 UPF Power Strategies 3.2 Succssively Refinable UPF 3.3 Incrementally Refinable UPF 3.4 Hierarchical UPF 4 Power Aware Standardization of Library 4.1 Liberty Power Management Attributes 4.2 Power Aware Verification Model Libraries 4.2.1 Non-PA Simulation Model Library 4.2.2 PA-Simulation Model Library 4.2.3 Extended-PA-Simulation Model Library 5 UPF Based Power Aware Dynamic Simulation 5.1 PA Dynamic Verification Techniques 5.2 PA Dynamic Simulation: Fundamentals 5.3 PA Dynamic Simulation: Verification Features 5.4 PA Dynamic Simulation: Verification Practices 5.5 PA Dynamic Simulation: Library Processing 5.6 PA Dynamic Simulation: Testbench Requirements 5.7 PA Dynamic Simulation: Custom PA Checkers and Monitors 5.8 PA Dynamic Simulation: Post-Synthesis Gate-Level Simulation 5.9 PA Dynamic Simulation: Simulation Results and Debugging Techniques 6 Power Aware Dynamic Simulation Coverage 6.1 PA Dynamic Simulation: Coverage Fundamentals 6.2 PA Dynamic Simulation : Coverage Features 6.3 PA Dynamic Simulation: Coverage Practices 6.3.1 Coverage Computation Model: For PA Dynamic Checks 6.3.2 Coverage Computation Model: For Power Stakes and Power State Transitions 6.3.3 Autotestplan Generation: From PA Dynamic Checks and Power State Transitions 6.3.4 Coverage Computation Model: For Cross-Coverage 7 UPF Based Power Aware Static Verification 7.1 PA Static Checks: Fundamental Techniques 7.2 PA Static Checks: Verification Features 7.3 PA Static Checks Library Processing 7.4 PA Static Checks: Verification Practices 7.5 PA Static Checks: Static Checker Results and Debugging Techniques 8 References.
Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base.
LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination.

The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r
egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers.

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