Behavioral Synthesis and Component Reuse with VHDL

Improvement in the quality of integrated circuit designs and a designer's productivity can be achieved by a combination of two factors:

• Using more structured design methodologies for extensive reuse of existing components and subsystems. It seems that 70% of new designs correspond to existing components that cannot be reused because of a lack of methodologies and tools.
• Providing higher level design tools allowing to start from a higher level of abstraction. After the success and the widespread acceptance of logic and RTL synthesis, the next step is behavioral synthesis, commonly called architectural or high-level synthesis.

Behavioral Synthesis and Component Reuse with VHDL provides methods and techniques for VHDL based behavioral synthesis and component reuse. The goal is to develop VHDL modeling strategies for emerging behavioral synthesis tools. Special attention is given to structured and modular design methods allowing hierarchical behavioral specification and design reuse. The goal of this book is not to discuss behavioral synthesis in general or to discuss a specific tool but to describe the specific issues related to behavioral synthesis of VHDL description.
This book targets designers who have to use behavioral synthesis tools or who wish to discover the real possibilities of this emerging technology. The book will also be of interest to teachers and students interested to learn or to teach VHDL based behavioral synthesis.

Springer Book Archives

1 Introduction.- 1.1 System Design: the Productivity Bottleneck.- 1.2 From Physical Design to System Design: Abstraction Levels.- 1.3 Behavioral Synthesis.- 1.4 Design Reuse.- 1.5 Component Reuse in VLSI.- 1.6 Modular Design Methodology for Component Reuse at the Behavioral Level.- 1.7 Summary.- 2 Models for Behavioral Synthesis.- 2.1 Design representation for behavioral synthesis.- 2.2 The datapath controller model.- 2.3 Datapath models.- 2.4 Controller models.- 2.5 Summary.- 3 VHDL Modeling for Behavioral Synthesis.- 3.1 Interpretation of VHDL descriptions.- 3.2 Behavioral VHDL execution modes.- 3.3 Scheduling VHDL descriptions.- 3.4 Summary.- 4 Behavioral VHDL Description Styles for Design Reuse.- 4.1 Design reuse.- 4.2 Design reuse at the behavioral level.- 4.3 Modular design.- 4.4 VHDL modeling for reuse.- 4.5 Towards object oriented design in VHDL.- 4.6 Summary.- 5 Anatomy of a Behavioral Synthesis System Based on VHDL.- 5.1 Main principles.- 5.2 Design steps and execution models.- 5.3 Interactive synthesis.- 5.4 Behavioral synthesis in the design loop.- 5.5 Summary.- 6 Case Study: Hierarchical Design Using Behavioral Synthesis.- 6.1 The PID.- 6.2 Specifications.- 6.3 System-level analysis and partitioning.- 6.4 Hierarchical Design.- 6.5 Design for reuse of the fixed-point unit as a behavioral component.- 6.6 Abstraction for reuse.- 6.7 Design reuse.- 6.8 The behavioral synthesis process.- 6.9 Summary.- 7 Case Study: Modular Design Using Behavioral Synthesis.- 7.1 Introduction.- 7.2 System specification.- 7.3 System partitioning.- 7.4 Behavioral specifications of subsystems.- 7.5 System design.- 7.6 Behavioral and RTL simulations.- 7.7 Summary.- References.